The present application relates generally to digital-to-analog converters, and more specifically to an area efficient piece-wise linear calibration technique for resistor string digital-to-analog converters.
Digital-to-analog converters (DACs) are known that employ resistor strings to convert digital input code values into analog output voltage levels. In a typical mode of operation, a conventional resistor string DAC receives digital code values at an input of the DAC, and employs a resistor string to convert the respective digital input code values into corresponding analog voltage levels at an output of the DAC. Each digital input code represents a quantized value, which is converted into a corresponding analog output voltage based on the transfer function of the DAC.
The conventional resistor string DAC includes a number of resistors connected in series, in which each resistor has a voltage tap at each of its ends. Further, the resistor string is typically biased at each of its opposing ends by two different reference voltages. For example, one reference voltage may be a positive voltage and the other reference voltage may be a negative voltage. Accordingly, the resistor string forms a voltage divider network, and each voltage tap of the resistor string is accessible to obtain a desired digital-to-analog conversion.
One drawback of the conventional resistor string DAC is that the offset, gain, and/or integral non-linearity of the DAC are typically imperfect. As a result, the analog output voltage produced by the DAC frequently has an error component, which prevents the amplitude of the DAC output voltage from directly corresponding to the magnitude of the digital code at the DAC input.
One way of improving the offset, gain, and integral non-linearity of the conventional resistor string DAC is to employ a digital calibration technique. For example, a conventional circuit for digitally calibrating a resistor string DAC may include a main DAC to be calibrated, a calibration DAC, a memory, and calibration logic circuitry for performing arithmetical operations. In a typical mode of operation, a plurality of integral non-linearity error values of the main DAC are determined, and the error values are coded into the memory as control points. Next, when a digital code value is applied to the main DAC input, a determination is made as to which two adjacent control points the input code lies between. A piecewise linear (PWL) function is then established between the two control points, and an error value is interpolated from the PWL function corresponding to the applied input code by the calibration logic. The interpolated error values are representative of an interpolated approximation of the main DAC's integral non-linearity curve. Next, the interpolated error value is applied to the input of the calibration DAC to produce a corresponding analog output voltage, which is subsequently subtracted from the output of the main DAC to remove the error component therefrom.
However, implementing the above-described conventional digital DAC calibration technique on an integrated circuit chip can be problematic, particularly in high voltage applications that employ large geometry process technology. This is because when such large geometry processes are employed, the amount of chip area required by the calibration logic circuitry for performing the PWL approximations can be relatively large, which can significantly increase costs. Another drawback is the need to provide analog calibration DACs, which can be imperfect.
It would therefore be desirable to have an improved calibration technique for digital-to-analog converters. Such a DAC calibration technique would be adaptable for calibrating DACs that employ resistor strings. It would also be desirable to have a DAC calibration technique that makes more efficient use of integrated circuit chip area.